Certain devices, such as a “computer on a chip”, are computing devices including, for example, a processor, a RAM for storing data, and a memory for storing code; the code which is loaded changes depending on the application. Since in some such devices the application executed by the device may vary, the size requirements for data and code segments may also vary.
Memories exist which provide for simultaneous access to memory data via two ports. However, such memories typically require that each memory cell include extra circuitry, beyond what is required in conventional memory cells. Such dual port memories may be expensive to construct, and may be larger in size than conventional memories. Furthermore, since such memories are not partitionable, such memories cannot respond to the varying code and data size requirements of devices that may be used with different applications.
Thus, a need exists for an inexpensive and size efficient memory providing simultaneous access to several partitions, where the size of the partitions may be varied.